| EE484 |
ADV CMPTR ARCHTR USG VHDL |
2010 |
1 |
Electrical Engineering and Computer Science |
3.0
(BS=0.0,
ET=3.0,
MA=0.0)
|
| The course builds on the computer architecture foundation provided in EE375. The functional block diagram approach and evolution into the Hardware Description Language paradigm, using the DOD-standard VHDL, introduced in the basic architecture course, is expanded to include advanced architectural issues. The reduced instruction set computer (RISC) architecture serves as the basis for the study of advanced issues. Emphasizing register transfer notation and behavioral modeling of discrete system components, hierarchical structure models of representative machines are designed and simulated. Cache memory, virtual memory, instruction pipelining, branch prediction, hazard avoidance and computer arithmetic are the major topics studied. The term project utilizes VHDL for the behavioral description of a processor and then proceeds through the use of CAD synthesis tools and system simulators. The Term Project is used in lieu of a Term End Examination. |
| 36 @ 55 min (2.500 Att/wk) |
4 @ 120 min |
|
|
Term design project using VHDL and FPGA's. Compensatory time given. |
| EE484 |
ADV CMPTR ARCHTR USG VHDL |
2005 |
1 |
Electrical Engineering and Computer Science |
3.0
(BS=0.0,
ET=3.0,
MA=0.0)
|
| The course builds on the computer architecture foundation provided in EE375. The functional block diagram approach and evolution into the Hardware Description Language paradigm, using the DOD-standard VHDL, introduced in the basic architecture course, is expanded to include advanced architectural issues. The reduced instruction set computer (RISC) architecture serves as the basis for the study of advanced issues. Emphasizing register transfer notation and behavioral modeling of discrete system components, hierarchical structure models of representative machines are designed and simulated. Cache memory, virtual memory, instruction pipelining, branch prediction, hazard avoidance and computer arithmetic are the major topics studied. The term project utilizes VHDL for the behavioral description of a processor and then proceeds through the use of CAD synthesis tools and system simulators. The Term Project is used in lieu of a Term End Examination. |
| 40 @ 55 min (2.500 Att/wk) |
0 @ 0 min |
|
|
Term design project using VHDL and FPGA's. Compensatory time given. |
| EE484 |
ADV CMPTR ARCHTR USG VHDL |
2003 |
2 |
Electrical Engineering and Computer Science |
3.0
(BS=0.0,
ET=3.0,
MA=0.0)
|
| The course builds on the computer architecture foundation provided in CS380 or EE475. The functional block diagram approach and evolution into the Hardware Description Language paradigm, using the DOD-standard VHDL, introduced in the basic architecture course, is expanded to include advanced architectural issues. The reduced instruction set computer (RISC) architecture serves as the basis for the study of advanced issues. Emphasizing register transfer notation and behavioral modeling of discrete system components, hierarchical structure models of representative machines are designed and simulated. Cache memory, virtual memory, instruction pipelining, branch prediction, hazard avoidance and computer arithmetic are the major topics studied. The term project utilizes VHDL for the behavioral description of a processor and then proceeds through the use of CAD synthesis tools and system simulators. The Term Project is used in lieu of a Term End Examination. |
| 40 @ 55 min (2.500 Att/wk) |
0 @ 0 min |
|
|
Term design project using VHDL and FPGA's. Compensatory time given. |
| EE484 |
ADV CMPTR ARCHTR USG VHDL |
1996 |
1 |
Electrical Engineering and Computer Science |
3.0
(BS=0.0,
ET=3.0,
MA=0.0)
|
| The course builds on the computer architecture foundation provided in CS380 or EE475. A functional block diagram approach evolves into the Hardware Description Language paradigm, using the DOD-standard VHDL. Emphasizing Register Transfer Notation and modeling fundamental processors as state machines, behavioral models are designed and built of representative machines. RISC architecture features are explored followed by a study of current CISC processors and advanced architectural issues. Cache memory, microprogram control, virtual memory, instruction pipelining, branch prediction and superscalar machines are just a few of the topics studied. Finally FPGAs are examined as tools for rapid prototyping in the development cycle, "Design - Design for Test - Simulate - Build - Test." The term project utilizes VHDL for the behavioral description of a processor and then proceeds through the use of CAD synthesis tools and system simulators. The Term Project is used in lieu of a Term End Examination. |
| 36 @ 55 min (2.500 Att/wk) |
4 @ 120 min |
|
|
Term design project using VHDL and FPGA's. Compensatory time given. |